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Sagot :
For an instruction-cache miss, data-cache miss, or TLB miss, the CPU must visit main memory. The third and easiest scenario is when the desired data is already present in a cache but the data needed for virtual-to-physical translation is not.
What do you mean by Translation Lookaside Buffer (TLB) ?
The most recent translations from virtual memory to physical memory are kept in a memory cache called a translation lookaside buffer (TLB). It is employed to speed up the process of accessing a user memory location. An address-translation cache is what it is.
- It is a component of the memory-management unit on the chip (MMU). Between the CPU and the CPU cache, between the CPU cache and the main memory, or between the several layers of the multi-level cache are possible locations for a TLB.
- TLBs are commonly found in the memory-management circuitry of desktop, laptop, and server CPUs, and they are almost always present in processors that use paged or segmented virtual memory.
To know more about TLB please click here ; https://brainly.com/question/19425406
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